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2009 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FT7521
Rev. 1.0.7
7
FT7521
—
Re
set
Ti
mer
with
Fi
x
ed
De
lay
and
Rese
t
Pulse
Physical Dimensions
Figure 6.
6-Lead, MicroPak
1.0 x 1.45 mm, JEDEC MO-252
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision.
Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the
warranty therein, which covers Fairchild products.
Always visit
Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
2. DIMENSIONS ARE IN MILLIMETERS
1. CONFORMS TO JEDEC STANDARD M0-252 VARIATION UAAD
4. FILENAME AND REVISION: MAC06AREV4
Notes:
3. DRAWING CONFORMS TO ASME Y14.5M-1994
TOP VIEW
RECOMMENED
LAND PATTERN
BOTTOM VIEW
1.45
1.00
A
B
0.05 C
2X
0.55MAX
0.05 C
(0.49)
(1)
(0.75)
(0.52)
(0.30)
6X
1X
6X
PIN 1
DETAIL A
0.075 X 45
CHAMFER
0.25
0.15
0.35
0.25
0.40
0.30
0.5
(0.05)
1.0
5X
DETAIL A
PIN 1 TERMINAL
0.40
0.30
0.45
0.35
0.10
0.00
0.10
C B A
0.05
C
0.05 C
0.05
0.00
5X
6X
(0.13)
4X
6X
PIN 1 IDENTIFIER
(0.254)
5. PIN ONE IDENTIFIER IS 2X LENGTH OF ANY
5
OTHER LINE IN THE MARK CODE LAYOUT.
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